1. Field of the Invention
The present invention relates to active pixel sensor cells and, more particularly, to an active pixel sensor cell that minimizes leakage current.
2. Description of the Related Art
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting a pixel of light energy into an electrical signal that represents the intensity of the light energy. In general, CCDs utilize a photogate to convert the light energy into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, which include a high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. Most notable among these weaknesses, which include limited readout rates and dynamic range limitations, is the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, more recent imaging circuits use active pixel sensor cells to convert a pixel of light energy into an electrical signal. With active pixel sensor cells, a conventional photodiode is typically combined with a number of active transistors which, in addition to forming an electrical signal, provide amplification, readout control, and reset control.
FIG. 1 shows a schematic diagram that illustrates a conventional CMOS active pixel sensor cell 10. As shown in FIG. 1, cell 10 includes a photodiode 12, a reset transistor 14, whose source is connected to photodiode 12, a source-follower transistor 16, whose gate is connected to photodiode 12, and a row-select transistor 18, whose drain is connected in series to the source of source-follower transistor 16.
Operation of active pixel sensor cell 10 is performed in three steps: a reset step, where cell 10 is reset from the previous integration cycle; an image integration step, where the light energy is collected and converted into an electrical signal; and a signal readout step, where the signal is read out.
As shown in FIG. 1, during the reset step, the gate of reset transistor 14 is briefly pulsed with a reset voltage V.sub.R (5 volts). The reset voltage V.sub.R turns on reset transistor 14 which pulls up the voltage on photodiode 12 and the gate of source-follower transistor 16 to an initial transfer voltage.
The initial transfer voltage placed on the gate of source-follower transistor 16 also defines an initial intermediate voltage on the source of source-follower transistor 16 which is one threshold voltage drop less than the initial transfer voltage.
Immediately after the gate of reset transistor 14 has been pulsed, the gate of row-select transistor 18 is pulsed with a row-select voltage V.sub.RS. The row-select voltage V.sub.RS on the gate of row-select transistor 18 causes the initial intermediate voltage on the source of source-follower transistor 16 to appear on the source of row-select transistor 18 as an initial integration voltage which, in turn, is read out and stored by an imaging system.
During integration, light energy, in the form of photons, strikes photodiode 12, thereby creating a number of electron-hole pairs. Photodiode 12 is designed to limit recombination between the newly formed electron-hole pairs.
As a result, the photogenerated holes are attracted to the ground terminal of photodiode 12, while the photogenerated electrons are attracted to the positive terminal of photodiode 12 where each additional electron reduces the voltage on photodiode 12.
Thus, at the end of the integration step, the potential on photodiode 12 and the gate of source-follower transistor 16 will have been reduced to a final transfer voltage where the amount of the reduction represents the intensity of the received light energy. As above, the final transfer voltage on the gate of source-follower transistor 16 defines a final intermediate voltage on the source of source-follower transistor 16.
Following the image integration period, the final intermediate voltage on the source of source-follower transistor 16 is then read out as a final integration voltage by again pulsing the gate of row-select transistor 18 with the row-select voltage V.sub.RS. As a result, a collected voltage which represents the total charge collected by cell 10 can be determined by subtracting the final integration voltage from the initial integration voltage.
FIG. 2 shows a plan view that illustrates a substrate level layout 100 of cell 10 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 3--3 of FIG. 2.
As shown in FIGS. 2 and 3, cell 10 of layout 100 is formed on a substrate 110 that includes an isolation region 112 defined by an outer wall portion 120 that encloses a plurality of active regions within substrate 110, and a protruding wall portion 122 that extends inward from the outer wall portion 120.
The protruding wall portion 122, in turn, divides the plurality of active regions into a first active region 130 on one side of wall portion 122, and second, third, and fourth active regions 132, 134, and 136 on an opposite side of wall portion 122. The first active region 130 of substrate 110 is doped with an n-type material to form an n+ photodiode 140, while the second, third, and fourth active regions 132, 134, and 136 are doped with an n-type material to form n+ source and drain regions for the transistors of cell 10.
Specifically, with reference to FIGS. 1 and 2, active region 132 functions as the source of select transistor 18, active region 134 functions as the source of sense transistor 16 and the drain of select transistor 18, and active region 136 functions as the drains for reset transistor 14 and sense transistor 16.
In addition, the second and third active regions 132 and 134 are separated by a select channel region 142, the third and fourth active regions 134 and 136 are separated by a sense channel region 144, and the first and fourth active regions 130 and 136 are separated by a reset channel region 146 defined between an end of the protruding wall portion 122 and the outer wall portion 120.
Further, isolation is provided by forming a field oxide region FOX in isolation region 112 of substrate 110. As shown, field oxide region FOX includes the well-known bird's beak 113 that results from the lateral expansion of the oxide during fabrication.
One problem with cell 10, however, is that cell 10 suffers from a leakage current which is most pronounced in the region where the active area contacts the bird's beak 113 of field oxide region FOX.
The leakage current in the bird's beak region is widely believed to be caused by lattice defects that occur during the formation of field oxide region FOX. These lattice defects create mid-band energy states that allow electrons from thermally-generated electron-hole pairs to more readily transition from the valence band to the conduction band. Once in the conduction band, these electrons contribute to the total photogenerated electrons, thereby adding an error term.
FIG. 4 shows a plan view of a substrate level layout 200 of cell 10 of FIG. 1 that illustrates a first technique for reducing the leakage current in the bird's beak region of field oxide region FOX. FIG. 5 is a cross-sectional view taken along line 5--5 of FIG. 4. As shown, layout 200 is structurally similar to layout 100 of FIG. 2 and, as a result, utilizes the same reference numerals to designate the structures which are common to both layouts.
As shown in FIGS. 4 and 5, layout 200 principally differs from layout 100 in that isolation is provided by a p+ region 145, which is positioned between surface regions 147 of substrate 110 in isolation region 112, in lieu of the field oxide region FOX of layout 100.
Although p+ region 145 provides satisfactory isolation, surface regions 147 of substrate 110 are also sources of a significant leakage current that results from defects at the substrate surface. These defects are typically caused by interface states that result from the use of an overlying layer of oxide.
In addition, surface regions 147 can not be eliminated by expanding the width of p+ region 145 to contact adjoining active regions (such as regions 130 and 132 in FIG. 5) because the resulting p+/n+ junction results in a strong electric field that also leads to a large leakage current.
FIG. 6 shows a plan view of a substrate level layout 300 of cell 10 of FIG. 1 that illustrates a second technique for reducing the leakage current in the bird's beak region of field oxide region FOX. FIG. 7 is a cross-sectional view taken along line 7--7 of FIG. 6. As shown, layout 300 is structurally similar to layout 100 of FIG. 2 and, as a result, utilizes the same reference numerals to designate the structures which are common to both layouts.
As shown in FIGS. 6 and 7, layout 300 principally differs from layout 100 in that isolation is provided by a polysilicon (poly) electrode 116, which is formed on a oxide layer 115 over isolation region 112, in lieu of the field oxide region FOX.
Specifically, isolation is provided by applying a negative voltage to poly electrode 116 which, in turn, causes holes to accumulate at the surface of isolation region 112. Although this approach, which is the subject of the '566 application, significantly reduces the leakage current, it is frequently a nuisance to provide a negative voltage. In addition, as discussed in the '191 application, single-poly implementations require more surface area, while double-poly implementations are more complex.
Thus, there is a need for an isolation technique that substantially reduces the leakage current without requiring the provision of a negative voltage.